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# Created by write_sdc on Mon Nov  6 15:42:34 2023

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set sdc_version 2.1

set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA
set_max_area 0
set_load -pin_load 0.2 [get_ports result]
set_ideal_network -no_propagate  [get_ports rst_n]
create_clock [get_ports clk]  -period 2  -waveform {0 1}
set_clock_latency -max 0.2  [get_clocks clk]
set_clock_latency -source 0.2  [get_clocks clk]
set_clock_uncertainty 0.1  [get_clocks clk]
set_clock_transition -max -rise 0.02 [get_clocks clk]
set_clock_transition -max -fall 0.02 [get_clocks clk]
set_clock_transition -min -rise 0.02 [get_clocks clk]
set_clock_transition -min -fall 0.02 [get_clocks clk]
set_false_path   -from [get_ports rst_n]
set_input_delay -clock clk  -max 0.8  [get_ports rst_n]
set_input_delay -clock clk  -min 0  [get_ports rst_n]
set_input_delay -clock clk  -max 0.8  [get_ports din_vld]
set_input_delay -clock clk  -min 0  [get_ports din_vld]
set_input_delay -clock clk  -max 0.8  [get_ports din]
set_input_delay -clock clk  -min 0  [get_ports din]
set_output_delay -clock clk  -max 0.8  [get_ports result]
set_output_delay -clock clk  -min 0  [get_ports result]
